On ARM Cortex-R4F, when I disable instruction and data cache using SCTLR register bits I and C, what happens to MPU region that defines region attribute as cachable (write-back)? Would it be ignored since global cache is disabled or would it result in unknown behavior?
Hi,
I think it would be ignored since global cache is disabled because I guess it would be the same as MMU (instead of PMU) case.
Best regards,
Yasuhiko Koumoto.
Pointer to ARM documentation at confirms the answer or any other insight would be helpful.
I'm sorry my memory was incorrect.With the setting of C=0 and M=1, the CPU habavior would be unpredictaable. This was not cleary described in recent manuals.I can refer to ARM926 TRM (ARM DDI0198D).
Best regards,Yasuhiko Koumoto.
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