Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

Yes and No. Mostly the second core is delayed a bit (IIRC, for TI's TMS570/RM4 it is half a clock cycle).

The reason is, that external effects (e.g. radiation) does not disturb both cores in the same state.

Yes and No. Mostly the second core is delayed a bit (IIRC, for TI's TMS570/RM4 it is half a clock cycle).

The reason is, that external effects (e.g. radiation) does not disturb both cores in the same state.