I have been trying to figure out when the unsupported exclusive data abort is actually raised in the ARM Cortex-R52 CPU.
From my understanding, it is not linked to an external resource such as DDR controller or L2 Cache Controller which does not implement a global monitor, and would therefore always respond with the OKAY status to the CPU on the AXI bus.
Instead, I suspect it is more linked to the implementation of the internal CPU logic to control exclusive accesses to private or external resources. As defined in the ARMv8-A architecture reference manual, this exception type is "implementation defined".
Is my understanding correct that "implementation defined" actually means this exception is triggered by the CPU internal logic itself when it detects exclusive access logic is not implemented?
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