I would like to switch from EL1 to EL0 and update my PC in one instruction because I would like to prevent code execution in EL0 mode in my supervisor memory zone.
In order to do that I would like to use ERET instruction or to pop CPSR from stack at boot time instead of using CPS instruction.
I didn't find in the documentation a specific reason to not use ERET at boot time but when I am using it (or when i amp poping cpsr from stack "pop pc^") the behavior is erroneous.
Thanks by advance,
Checkout "RFE" instruction.
First of all, thank you for you answer.
RFE gives the same result as eret (or movs pc,lr) at boot time (I tried it yesterday).
It is really strange because I do these operations (changing spsr during exception handler) after booting and they work as as expected. They behave badly only at boot time. The CPSR and pc are correct after the call to eret/rfe/pop/movs but processor has unpredictible behavior. The only way i found to go to user mode by loading CPSR and pc in one instruction at boot time is to trigger an exception (by doing an hvc for example) and return from it.
What core are you on? Sounds like a Armv8-R core?
yes! I am on a R52. Did you know the explanation on what is going on?
I have no experience with Armv8-R, but on Armv7-R I just make a "refia sp!" to switch to EL0. Are you sure you are not in EL2? You say "directly after boot", so I'd assume the core boots in EL2.
I am doing a first eret to jump to el1, then i am loading lrand spsr to do a second eret. After this point the software become unstable. Another company (which is specialized in rtos) has encountered the same problem. We will ask the manufacturer. If you are interested i can forward you the answers. For the moment i trig an hvc as a workaround.
Sure, though I haven't seen the r52 in the wild (guess it is an automotive chip), you can PM me the outcome. I am a hunter and collector of such infos.