There are two questions about coherence between R82 and others as:
R82 only with a ACE5-LITE interface
In the public datasheet of Cortex-R82
Cortex-R82 can support AXI or CHI-E Main Master port, if CHI-E is used, then with coherent interconnect, it supports hardware coherency for multiple Cortex-R82 clusters or Cortex-A clusters.
If you were talking about the cache coherency within cores in one Cortex-R82 cluster, then L2 memory system in the cluster is able to maintain cache coherency between them.
If using Cortex-R82 ACP port, an ACE5-Lite 128-bit shared slave main Accelerator Coherency Port (ACP) for external access to MM address ranges. ACP enables I/O coherency for external agents with the per-core L1 data cache and shared L2 cache.
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