How to test " Lock-Step " is working on Cortex-R5 ?

The comparison logic and error signalling mechanism is something that may be specific to each silicon partners implementation, particularly any test (or error injection) mechanisms for the comparison logic. I suggest you look at your silicon providers technical reference documentation.

regards,

Jon

The comparison logic and error signalling mechanism is something that may be specific to each silicon partners implementation, particularly any test (or error injection) mechanisms for the comparison logic. I suggest you look at your silicon providers technical reference documentation.

regards,

Jon