ATCM ECC error causes prefetch abort despite ECC check being disabled.

Hello,

I am working with TI's TMS570LS3137 (ARM Cortex R4F).

A certain part of my code consistently causes a prefetch abort (I say part because the exact location seems to vary slightly).

To try and identify the cause I set a breakpoint at the prefetch abort handler (0x0000000C) and looked at the following registers:

  • r14_abt = 0x10
    • Here I would expect to see the value of the link register when the abort occured. 0x10 makes no sense to me as that is the address of the data abort vector.
  • IFAR (Instruction Fault Address Register) = 0x0000000C
    • The abort occured when trying to execute from address 0x0000000C. At no point does my code ever attempt to execute from that address.
  • IFSR (Instruction Fault Status Register) = 0x00000409
    • The cause of the abort was a Synchronous Parity/ECC error.
  • AIFSR (Auxiliary Instruction Fault Status Register) = 0x00400000
    • The error occured in ATCM. This should not be possible as I have disabled the CPU's parity/ECC check for both ATCM & BTCM by clearing ATCMPCEN, B0TCMPCEN and B1TCMPCEN

Here is how I disabled parity/ECC check:

// Disable CPU parity/ECC check
asm(" PUSH {r1}");
asm(" MRC p15, #0, r1, c1, c0, #1");    // Read ACTLR
asm(" BIC r1, r1, #0x0E000000");        // Clear ATCMPCEN, B0TCMPCEN, B1TCMPCEN
asm(" MCR p15, #0, r1, c1, c0, #1");    // Write ACTLR
asm(" POP {r1}");

These observations leave me with two questions:

  1. Am I misinterpreting the value of r14_abt & IFAR?
  2. Am I not disabling parity/ECC check correctly?

Thank you in advance

  • Little unrelated, but: You should not use multiple asm() statements if you want the code be placed the way you wrote it:

    asm(" PUSH {r1}\n"
        " MRC p15, #0, r1, c1, c0, #1\n"    /* Read ACTLR */
        " BIC r1, r1, #0x0E000000\n"        /* Clear ATCMPCEN, B0TCMPCEN, B1TCMPCEN */
        " MCR p15, #0, r1, c1, c0, #1\n"    /* Write ACTLR */
        " POP {r1}");

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