On an exising project based on Cortex-R5, with a limited ATCM/BTCM resources, we need to start using Data/Instruction Cache with DDR (DRAM), to improve performance.
There is a lot scattered info in ARM documentation about caches - can you point me to some Refrence Code for:
1. Data/instruction Cache configuration during startup?
2. Data/instruction Cache configuration during run-time?
WRT Specific considerations using Data/Instruction Cache- can you point me to some documentation & Reference Code for:
3. Guidelines & Reference Code for CODE that one should keep in ATCM (typically holds interrupt or exception code that must be accessed at high speed,without any potential delay resulting from a cache miss), while using Data/Instruction Cache, and interactions with code/data in Instruction/Data Cache?
4. Guidelines & Reference Code for DATA that one should keep in BTCM (typically holds any block of data for intensive processing, such as audio or videoprocessing), while using Data/Instruction Cache, and interactions with data/code in Data/Instruction Cache?
5. Guidelines & Reference Code for CODE/DATA in Data/Instruction Cache, when RTOS is involved?
6. Guidelines & Reference Code for CODE/DATA in Data/Instruction Cache, when DMA is involved?
A quick answer to 1) and 2) would be to download Arm Developer Studio (an evaluation licence will work for this) and included in the install is example start up code for R5 that enables the cache.
I'm not aware of any reference code that covers the other questions, but someone else might be more knowledgeable.
Hi Pete, I will try it, thanks!
Anyone else regarding items 3,4,5?
No guide lines. Only: In general, the RTOS does not care for the caches. If you use DMA you must be aware that it is "Direct", means it does not use the caches and (unless there is a snoop logic) the caches will not know if memory was modified by the DMA.
Thanks, Bastian, It is a wonder how no guidelines/examples, but ok, we'll look carefully on that, once we get to implement DMA, and how to let caches be "aware" of DMA modifications.
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