Embedded SW cannot set CPSR.F for obvious reasons. However, for test purposes, it is needed that the debug interface has access to set CPSR.F (e.g. to make sure the SW correctly clears it). Is it possible to set CPSR.F through debug port for Cortex-R5F? It is not clear in the TRM documentation.
If FIQ is used as NMI the F bit can only be cleared. If you set it with a debugger, it will fall back to 0 after the CPU runs.
On systems with TrustZone (Cortex-A9), it can be set persistently in Monitor mode.
Thanks for your reply. But it's there a debugger-specific backdoor port that allows a debugger to do more than what SW can do?
If not, I don't know how we'll perform our tests... We must make sure our SW correctly clear the F bit; for that, our test procedure needs to set it...
We do a similar test for SCIOPTA. Upon reset the F bit is set. So, check this, clear it, check again. Test passed.
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