Is it OK to bypass all clock gates in Cortex-R52?


I am doing FPGA prototyping for an SoC. There is a Cortex-R52 in the IP that needs to be prototyped on FPGA.

I cannot close timing with all the clock gates inside R52 enabled. Can I bypass them and assign clock_out = clock_in, without affecting R52's functionality?

Since it's FPGA prototyping, scenarios like power gating and turning submodules to sleep mode need not be exercised on FPGA.