PMU Register description is not clear in Arm Cortex -R52 Processor Revision: r1p1

Hi ,

I am NXP working for functional validation group and writing PMU API but facing issue for detailed description of many of the PMU registers .

I am referring to "Arm® Cortex®-R52 Processor Revision: r1p1".Many places UNK is written for reset values and description is not given.

can u please help me to get the detailed documentation for PMU v3.

Regards,

Ankur Kumar