When is Cortex-R5 Virtual Peripheral AXI bus used?

The Cortex-R5 has a single AXI peripheral physical bus which is divided into a LLPP Normal AXI interface and an LLPP Virtual AXI interface. The TRM document also explains that ordering is disconnected between these 2 interfaces. Fine.

However, I am not able to find WHEN an access to a peripheral register will be routed through the Normal or the Virtual AXI interface. How is it selected?

I know the Virual AXI interface can be enabled through the Peripheral interface region register ("En" field). But once both interfaces are enabled, which will take care of accesses? On my CPU, both interfaces have the same size and base address.