I have a Cortex-R5F core in which integration register value CPACR.ASEDIS = 1 and CPACR.D32DIS = 1m which says Advanced SIMD is not available. However, in ARM Cortex-R5F Technical Reference Manual revision r1p2, §2.1.2 "ARM architecture", it says:
The Cortex-R5 processor implements the ARMv7-R architecture profile that includes thefollowing architecture extensions:• Advanced Single Instruction Multiple Data (SIMD) architecture extension for integer andfloating-point vector operations
Who is right? Is Advanced SIMD supported or not?
Also, I am a bit confused between "Advanced SIMD" and "SIMD". Register ID_ISAR3.SIMD_instructions = 0x3, which means a bunch of SIMD instructions are enabled:
PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX,SHSUB16, SHSUB8, SHSAX, SSAT, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16,UHADD8, UASX, UHSUB16, UHSUB8, USAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT,USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16, and the GE[3:0] bits in the PSRs.
I understand that these are like normal SIMD instructions, but that it excludes "Advanced SIMD" instructions. Am I right?
Thanks for reporting this error. You are correct that Cortex-R5 implements SIMD, but not Advanced SIMD (NEON). (Advanced SIMD is introduced in Cortex-R52, Armv8-R).
For reference, the error is in section 1.2.1, not 2.1.2 (I guess that is a typo). The same error is found in Cortex-R4 TRM.
Hi, Is it possible to run Cortex-M SIMD instruction on Cortex-R to reuse the existing code from Cortex-M to Cortex-R4 after recompilation?
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