Cache ECC in Cortex-R5 & Event bus

Hi everybody,

I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery".

As far as I understand, in that mode, as the memory is in write-through, ECC errors are always correctable since the stored data in cache is also stored in the L2RAM. So when an uncorrectable ECC is detected in cache, the line is only invalidated and the correct data data is reloaded from the L2 memory (no data is lost).

That is perfect to make ECC uncorrectable errors transparent to the system and increase the availability.

But then I saw that the event bus also outputs the "data cache data RAM uncorrectable ECC" as an event, and in the TMS570LC4357, this information is used by the Error Signalling Module (ESM) to generate a system error (output on the nERROR pin) automatically when it occurs, as soon as the events are exported (through PMCR register, bit X).

Can anyone confirm or explain to me if I am correct on that point? If an uncorrectable ECC occurs in data cache, event if the "Do not generate abort, force write-through, enable hardware recovery" is selected, errors will lead to a ESM group 3 channel 9 error in the TMS570LC4357?

Thank you,

Gael

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