• "BX LR" causing INVPC Usage Fault exception

    I have implemented a context switching code. For going back to privileged user mode after setting the return value in SP + 0x18 address, I am using BX LR instruction.

    But code execution goes to HardFault handler and INVPC bit of USAFAULT register is set…

  • arm-none-eabi-gcc (bleeding-edge-toolchain) 9.1.0

    I've just created another release of my bleeding-edge-toolchain script, which builds a complete toolchain for ARM microcontrollers. This toolchain uses the most recent versions of all possible components:

    • gcc-9.1.0
    • newlib-3.1.0
    • binutils-2.32
    • gdb…

  • Setting up an ISR for a PIT timer (homework help)

    Hello,

    I'm in a course in which we are supposed to learn to program an (ARM) microcontroller. This is my sixth homework task. I'm fairly new to assembler-programming, but so far I've managed to work out all tasks with the help of the internet, different…

  • System Bus in ARM Cortex-M4

    In what situations will separate data buses ( D and S) for ARM Cortex-M4 improve performance? Also, are there any benefits of von Neuman support along with the core Harvard Architecture?