• What's happening if NMI is active (via a push-button) during µC (Cortex M4) start-up (power on)?

    Hi everyone,

    I need help about NMI that seems to freeze mu µC during power on.

    I use a cortex M4 ( K64 from NXP/Freescale ). On the board I use, the NMI is connected to a push button.

    If I don't press the NMI button, my software run.

    If I press…

  • Linker in gnu arm toolchain says "group ended without start" thought there is no such option in my build

    shyam@shyam:~/projects/zynq/microzed/linux_source/Test_Chips$ make
    make -C  /home/shyam/projects/zynq/microzed/linux_source/Test_Chips/../dev_tools/build
    make[1]: Entering directory `/home/shyam/projects/zynq/microzed/linux_source/dev_tools/build'
    Making…

  • undefined reference to `atan2'

    Former Member
    Former Member

    Hi Friends ,

    I need to fix this problem and I've read something about gcc but I didnt understand how can I do it.

    [cc] C:\Users\Emrah\Desktop\imu_STM32F407\imu\Src/main.c:39: undefined reference to `atan2'
    [cc] collect2.exe: error: ld returned…

  • CMSIS DSP - Realtime FIR Filter, Sample by Sample Issue

    I'm trying to implement a realtime lowpass FIR filter using the CMSIS library.

    I'm essentially following this example:

    The only difference is that instead of running the filter on a block of samples, I want to run the filter sample by sample.…

  • Setting up an ISR for a PIT timer (homework help)

    Hello,

    I'm in a course in which we are supposed to learn to program an (ARM) microcontroller. This is my sixth homework task. I'm fairly new to assembler-programming, but so far I've managed to work out all tasks with the help of the internet, different…

  • Help with programming STM32F103RCT6 board.

    I have bought  this Cortex M3 board. Now I want to program it through jtag.

    So I bought this wire. By using the USB to serial interface of my linux machine, I want to program the board.

    I went to read the data sheet of board here[1]. In section 2.3.29…

  • Stable set of ARM MCU, libraries, and Dev Environment

    Hi,

    I tried to get into this a year ago and ran out of time, here I go again... and I hope this isn't too opinion based, the state of IDEs and libraries should be clear (in flux or stable)

    I'm looking for a stable set of ARM MCU, libraries, and dev…

  • Cache attribute write back/write allocate for Cortex-M4

    What is different between write back with write allocate and write with non write allocate on Cortex-M4.

  • Program ARM-device from Linux

    Hello everyone!

    I want to buy STM32F103C8T6 and my os is Ubuntu and I don't want to use IDEs. I already found the developer's tools - GNU Arm Embedded Toolchain, but have the question - there is a suitable linux software to program ARM devices…

  • Blink Newbie help debug!

    Hi Forum.

    I'm new to ARM, but have experience with AVR. I'm just trying to make a Hello World with blinky LEDs. I have this board:

    https://forum.micropython.org/viewtopic.php?t=3086

    So ok, everything seems to be setup right. I can compile and…

  • Gcc naked attribute leaves some trailing function prologue asm instructions

      I've the following implementation for a svc exception handler on a cortex-m0:

        int  __attribute__((naked))  
        sv_call_handler(uint32_t n, uint32_t arg1, uint32_t arg2, uint32_t arg3,  
                        uint32_t arg4, uint32_t arg5)
         {
              irq_off();


    When I built it for cortex…

  • instructions fetch

    Hello, when I use stm32f103xx, I am confused of  one of the boot modes it supported. One of  the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots from SRAM,  how Cortex-M3 fetches instructions…

  • Cortex-M0+ JTAG state doesn't reset in simulation when tying nTRST high and trying synchronously reset through TMS

    Hi,

    According to the Cortex M0+ integration guide: "nTRST can be tied HIGH when a synchronous JTAG reset is
    provided through the TMS pin."

    However in simulation the JTAG state is constant 'X' and can't be reset through TMS.

    Can you…

  • CortexM4:How to change the entrypoint by binary file data in the program

    Hello.

    There is an executable file built by setting the address of the entry point (RO_Base) to 0x00000000 with Keil's linker setting.

    I converted this executable file into plain binary format data using "fromelf - bin" command.

    This binary…

  • Cortex M4: Atomic and Cache

    Hello all,

           Recently I came across this issue for the cortex M4 core.

           We are running a freertos application which loads and stores the value of a variable.

           For this we are using the atomic functions like atomic_load, atomic_store and atomic_compare_exchange_strong…

  • Hard Faults and MemManage Faults in Cortex m3/m4

    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated. But in my case hardfault is also not triggering.

    Here…

  • Store the value of PC to Memory address

    I want to store the value of Program Counter(pc) to a memory location.

    I did this, 

        LDR R1, =[0x20000000]

        STR R15, [R1,#0]

    I got an error saying, "Error: r15(pc) not allowed here -- `str R15,[R1,#0]'.

    How should I get over this error?

  • Cycle accurate simulator/emulator for a Cortex M4 processor based board

    Hi all,

    I am  a master student in germany and doing my thesis currently. I wanted to measure CPU cycles using emulation/simulation for some code that is running on a cortex m4F processor based board. I had QEMU in mind at initial but it turns out it doesn…

  • the means of tail-chaining of interrupts

    hellow

         I am reading the book  “Cortex  -M3 Embedded Software Development” on page of 3,chapter 1.1 Nested Vectored Interrupt Controller (NVIC),

    i don not understand  the means of tail-chaining of interrupts .In the sentence of  "The NVIC also…

  • Cortex M7 D cache activated without MPU been enabled

    Hi,

    I have question related to cortex M7 cache behavior.

    I noticed that whenever the MPU is disabled after power on reset then I activate data cache I get a hardfault (data cache is already invalidated before enabling data cache).

    This doesn't make sense…

  • M0 Analog-Digital Conversion info needed

    I have had a remarkable lack of success trying to locate information about the M0 ADC.  I need to know

    • The capacitor value, in nf or pf
    • The duration of the "sampling aperture"
    • The min/typ/max power required to get a valid sample

    I want to…

  • Where can i find resources about creating program on cortex-m7 from scratch?

    I want to make full process with my hands: writing startup, linker script, init file, makefile configurate toolset and so far and so forth.

  • Memory related issue with MCU startup ( __libc_init_array )

    Dear Community,

    I am developing firmware for STM32l476VGT using Gnu Make Builder and "Ac6 STM32 MCU GCC" Toolchain. I encounter a memory related run time error during the startup (before main) of my controller. The error occurs during the execution of…

  • Understanding of the clock cycle activity for LPC1114

    Hello, 

    I am now working with the LPC1114 which utilizes the ARM CORTEX M0 architecture. I have one question about the instruction set summary of the ARMv6M Thumb instruction set. I want to know what the processor does during each single clock cycle for…

  • i2c LPC1788 interface with raspberry pi3

    Greetings ARM peoples

    I am trying to interface LPC1788 with Raspberry Pi3 through I2C.

    Raspberry Pi will be master and LPC will be slave (More LPC slaves have to be added in future)

    Raspberry will send set of data to LPC and LPC will generted output for…