• External Private Peripheral Bus

    Hi!

    What is exact differences between IPPB (Internal Private Peripheral Bus) and EPPB (External Private Peripheral Bus)?

    I think that IPPB peripherals and components are inside the processor (Cortex-M3/M4 core etc.) but, the EPPB peripherals and components…

  • timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)

    I am trying to find the location of the register where the timestamp generator can be enabled on a Cortex-M4 processor.

    In the CoreSight SoC Technical Reference Manual on page 3-210 it is mentioned that the register (CNTCR) is in the PSELCTRL region…

  • A panic function to halt the processor in low-power sleep using WFI?

    As part of fault detection / debugging, it's useful to have a panic() function that halts the processor.

    It is easy enough to disable interrupts and put the processor in an infinite busy loop (while (1)). However, that burns power, and I am looking…