Hi to you all,I've a firmware running on a NXP LPCLink2 (LPC4370: 204 Mhz Cortex M4 MCU) board which basically does this:
My problem is that my code is too slow, and every now and then and overwrite occurs.
Using the DMA I'm saving the ADC data, which I get in Twos complement format (Offset binary is also available), in a uint32_t buffer and try to prepare them for the CMSIS DSP function by converting the buffer into float32_t: here's where the overwrite occurs. It's worth saying that I'm currently using Floating point Software, not hardware.
The CMSIS library also accepts fractional formats like q31_t, q15_t and so on, and since I don't strictly need floating point maths I could even use these formats if that could save me precious time.It feels like I'm missing something important about this step, that's no surprise since this is my first project on a complex MCU, any help/hint/advise would be highly appreciated and would help me in my thesis.
I'll leave here the link for the (more datailed) question I asked in the NXP forums, just in case: LPC4370: ADCHS, GPDMA and CMSIS DSP | NXP Community .
Thanks in advance!
Good post goodwin!
goodwin wrote: (adcBuff[i] << 20) >> 20I just can't clearly recall if I previously encountered a compiler which cancels opposing shifts like this.
goodwin wrote:
(adcBuff[i] << 20) >> 20
I just can't clearly recall if I previously encountered a compiler which cancels opposing shifts like this.
Such compilers are faulty and would generate incorrect code.
The compiler is free to optimize the code, however, making the code behave incorrectly is not allowed.
An exception: If the resulting value of the shift is unused, then of course the compiler is allowed to remove it completely.
Another exception: If the compiler can 'see' that only the low 12 bits are used anyway, it is free to ignore the line completely (GCC is capable of doing that, as the optimizer is very sophisticated).
I would expect that an optimizing compiler would reduce the above to a single instruction:
... for signed values ...
sbfx rT,rS,0,12
... and for unsigned values ...
ubfx rT,rS,0,12
-I know that GCC is working well, regarding optimizing and code reduction.
Such compilers are faulty and would generate incorrect code.The compiler is free to optimize the code, however, making the code behave incorrectly is not allowed.
If there is really a compiler that behaves like that, the author unintentionally neglected the signed (integral) nature of the variable.
When portability (especially to other architecture) is not a consideration, it may be better to use the bitfield instruction directly rather than the shift operator.
If the right-shift and left-shift counts are the same, then yes, the sbfx would certainly be the best choice; it cost only one clock cycle.
If, however, converting to fixed point, the sbfx instruction won't be able to do it on its own.
This is because the left-shift and right-shift counts would differ.
As sbfx is a wide instruction (it spans two 16-bit words) and shifting only spans one 16-bit word, they will shorten the used program space (and be a little more cache-friendly; a marginal improvement, but it could help preventing hickups).
Two shift operations will still cost 2 clock cycles. There's another advantage: You do not have to worry about 32-bit alignment when you use a 16-bit instruction. I've experienced performance decrease if a 32-bit instruction is on not on a 32-bit boundary (performance decrease in the form of stalls).
This is an advanced topic, which I hope to cover in a document I plan on writing on how to use the IT instruction more efficiently.