When a interrupt occurs, ARM documentation(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/3682.html) says interrupt is disabled till the very end of handlers. When the ARM documentation says that the processor automatically disables the single "Normal IRQ" interrupt, is it the case that all interrupts mapped (via the ARM Interrupt Controller) to the single IRQ gets disabled, or just the one interrupt which was raised is disabled ?
Hello,
"Upon entry to the IRQ exception handler, the 'I' bit is set (of the CPSR)." means all IRQs are masked in the IRQ exception handler.
Best regards,
Yasuhiko Koumoto.
Very good and interesting question, msd - and a very good answer, yasuhikokoumoto.
jyiu once wrote that interrupts can be nested, thus an interrupt can be interrupted (even during the stacking event).
(see A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the ARM® Cortex®-M processors).
I would expect that SysTick is not considered an IRQ interrupt, so I perhaps SysTick is able to periodically trigger while inside an IRQ interurpt-handler. (jyiu, please correct me if I'm wrong here).
I think I might have seen the SysTick occur while inside another interrupt - but I am not 100% sure.
I guess the original question is related to classic ARM processors (e.g. ARM7TDMI). Newer Cortex-M processor support nested interrupts in its hardware.
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