Hi all,
I did some of the investigation based on comparison of FPU based algorithms on CM4 and CM7 cores. All the code/data were placed into the single cycle memory with full utilization of modified / true Harvard architecture, it means:
- on CM4 - code in SRAM accesible via CODE bus, data in SRAM accesible via SYSTEM bus with fully utilized modified Harvard architecture
- on CM7 - code in I-TCM memory, data in DTCM memory
Most of the code (instructions) are floating point (99%), it means thay are not interleaved with integer instructions (well this is most probably caused by compiler - to be honest I have check the assembly for both codes CM4 / CM7 and they looked the same). The code mostly contains general math calculations mul, mac, sqrt, div + load / store, all in floating point. The result I am getting are confusing me. Cortex M4 shows even better results that Cortex M7.
Questions:
- are the differencies caused by cores pipelines? not sure how "dynamic branch prediction" works, if it is really posible to get branch in single cycle or it is required to flush whole pipeline (6 cycles) in a case of floating point pipeline on CM7
- what are the best practices in coding to get the best from CM7 over CM4 in floating point meaning? (not sure if the compilers are now in best condition regarding to CM7)
thanks in advance.
regards
Rastislav
Hello Rastislav,
I have gotten the STM32F7 Discovery board and now I can cross-check your results.
Can you provide the codes of which performance were less than Cortex-M7?
For a trial, I measured the 4x4 matrix multiply performance of the floating point by SysTick.
The results are
Cortex-M7: 303 cpu cycles and
Cortex-M4: 452 cpu cycles.
According to my trial, Cortex-M7 is 1.5 times better performance than Cortex-M4.
Best regards,
Yasuhiko Koumoto.
Hi Yasuhiko san,
Very much appropriate your help with. I am on vacation nowadays with limited access to the evaluation. However, after vacation I will try also your test (higher level of matrix). Thanks.
Regards
Od: yasuhikokoumoto
Odoslané: Sunday, July 26, 2015 23:17
Komu: Pavlanin Rastislav-B34185
Predmet: Re: - What is the advantage of floating point of CM7 versus CM4
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What is the advantage of floating point of CM7 versus CM4
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I also measured performance of Linpack and Whetstone benchmarks.
Linpack: 1.62 times faster by Cortex-M7 at the same clock.
Whetsone: 1.91 times faster by Cortex-M7 at the same clock.
Hello,
I tried to reply earlier, but I think I accidentally closed the window
.... or maybe you will see 2 replies.
These results are broadly what we would expect.
Linpack, whetstone and matrix multiply are all long enough and varied enough code to benefit from Cortex-M7's microarchitecture.
The short instruction sequence to approximate cos will execute roughly the same on Cortex-M4 and Cortex-M7 - you gain a little from dual issue of the loads, but then lose a little from dependencies between the FP arithmetic instructions.
You may get slightly different results using the ARM compiler, but there is not much chance for the compiler to avoid the dependencies in such a short sequence.
Ian
I'm not ignoring you but we have the ARM Partner's meeting in Cambridge this week.
I'll talk to our engineering team and get back to you.
Hello Ian,
what is your opinion about the issue?
I evaluated again from another aspect.
This time, I prepared the following 3 functions.
The C source code is below.
float ip(float a, float b, float c, float d, float e) { float x,y,z,u,v; x=a*a; y=b*b; z=c*c; u=d*d; v=e*e; return (float)(x+y+z+z+u+v); }
And I compiled it by 3 different optimization options.
Ip0 is for Cortex-M3.
Ip1 is for Cortex-M7.
Ip2 is for Cortex-R7 (same as Cortex-A9).
float ip0(float a, float b, float c, float d, float e) { asm("vmul.f32 s1, s1, s1"); asm("vmul.f32 s0, s0, s0"); asm("vmul.f32 s2, s2, s2"); asm("vadd.f32 s0, s0, s1"); asm("vmul.f32 s3, s3, s3"); asm("vadd.f32 s0, s0, s2"); asm("vmul.f32 s4, s4, s4"); asm("vadd.f32 s0, s0, s2"); asm("vadd.f32 s0, s0, s3"); asm("vadd.f32 s0, s0, s4"); asm("bx lr"); asm("nop"); }
float ip1(float a, float b, float c, float d, float e) { asm("vmul.f32 s0, s0, s0"); asm("vmul.f32 s1, s1, s1"); asm("vmul.f32 s2, s2, s2"); asm("vmul.f32 s3, s3, s3"); asm("vadd.f32 s1, s0, s1"); asm("vmul.f32 s4, s4, s4"); asm("vadd.f32 s1, s1, s2"); asm("vadd.f32 s1, s1, s2"); asm("vadd.f32 s0, s1, s3"); asm("vadd.f32 s0, s0, s4"); asm("bx lr"); asm("nop"); }
float ip2(float a, float b, float c, float d, float e) { asm("vmul.f32 s1, s1, s1"); asm("vmul.f32 s2, s2, s2"); asm("vmla.f32 s1, s0, s0"); asm("vadd.f32 s0, s1, s2"); asm("vadd.f32 s0, s0, s2"); asm("vmla.f32 s0, s3, s3"); asm("vmla.f32 s0, s4, s4"); asm("bx lr"); asm("nop"); }
Ip0 and ip1 are the same but the instruction order is different.
Ip1 has less dependency of registers.
Ip2 is just for the information and it uses the multiply and addition instructions.
The execution time by Cortex-M7 and Cortex-M4 will be shown below.
- Cortex-M7
ip0 40 cycles
ip1 33 cycles
ip2 27 cycles
- Cortex-M4
ip0 32 cycles
ip1 37 cycles
ip2 30 cycles
The results show the register dependency will affect the performance.
However, by using each specific compile option, the best performance will be gotten.
Hi Yasuhiko,
Yes, this is quite interesting investigation. I have also done some of the test which are based on different compilers (ICCCARM, ARMCC), different optimization etc. and then using inline assembler to play with order of instruction in the code execution. Play with the mixing fixed / floating point operations. However, at the end the best results I have got considering floating point operation were achieved on CM4. In all configuration mentioned the same mathematical calculation (with the same parameters and coefficients) were used. Of course in some special cases CM7 showed better results than CM4. However, the best results were achieved on CM4. I getting to be sure that the compiler are not yet prepared to CM7 features. It would be perfect to have definitive answer from ARM to show us how to write a code / use a compiler to utilize CM7 full performance.
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