How to acknowledge/clear active interrupt in Cortex-M4

Hi all,

I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to NVIC is de-asserted, the handler is called again. At this point I can see that NVIC_ISPR0(interrupt pending register) is 0, but the corresponding bit in NVIC_IABR0(interrupt active register) is set. The handler is called a couple of times more, and after that the pin to NVIC is de-asserted and I can see NVIC_IABR0 is 0 now.

Do I have to manually clear NVIC_IABR0 inside my handler? I think it is a read-only register.

Is there any other way to "acknowledge" this interrupt and tell CPU that I have services it(like reading IACK reg in Cortex A-53)?

Thanks a lot for your help. Please excuse if the question sounds too trivial.

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  • Hello.

    as you say, NVIC_IABR0 is a read only register.

    I guess you will clear the interrupt source from the peripheral in the interrupt handler.

    At the entry point  of the handler, NVIC_ISPR0 would be 0, because the activated interrupt would be cleared automatically at the entry point.

    However, if your clearing of the interrupt source was delayed, NVIC would accept the same interrupt again.

    Therefore you should write NVIC_ICPR0 to clear the 2nd interrupt after clearing the interrupt source.

    Does this help you?

    Best regards,

    Yasuhiko Koumoto.

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  • Hello.

    as you say, NVIC_IABR0 is a read only register.

    I guess you will clear the interrupt source from the peripheral in the interrupt handler.

    At the entry point  of the handler, NVIC_ISPR0 would be 0, because the activated interrupt would be cleared automatically at the entry point.

    However, if your clearing of the interrupt source was delayed, NVIC would accept the same interrupt again.

    Therefore you should write NVIC_ICPR0 to clear the 2nd interrupt after clearing the interrupt source.

    Does this help you?

    Best regards,

    Yasuhiko Koumoto.

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