Hello experts,
recently ARM updated the Cortex-M7 information.
I think the biggest topic would be that the pipeline details were opened.
The new information says that the integer pipeline is 4 stage and the floating point pipeline is 5 stage.
However, the past information said that it was 6 stage.
From where this differences came?
I would like to know the concrete explanation for each stage.
What is the first stage, what is the second stage, what is the third stage, what is the fourth stage, and so on?
Best regards,
Yasuhiko Koumoto.
Sorry, I am not an ARM employee just a partner. We are not using Cortex-M7 currently but we are definitely interested in it because of the potential big performance improvement over Cortex-M4. There are not that many commercially available M7 anyway.
The MAC is actually a 5-stage pipeline. You forgot the Instruction Fetch stage.
Getting an answer from ARM would be really nice. Is there a way to poke an ARM FAE with these specific questions? We've just recently joined the ARM community so not very familiar with the protocol.
Best,
HBL