Hello experts,
recently ARM updated the Cortex-M7 information.
I think the biggest topic would be that the pipeline details were opened.
The new information says that the integer pipeline is 4 stage and the floating point pipeline is 5 stage.
However, the past information said that it was 6 stage.
From where this differences came?
I would like to know the concrete explanation for each stage.
What is the first stage, what is the second stage, what is the third stage, what is the fourth stage, and so on?
Best regards,
Yasuhiko Koumoto.
Hello,
I found the below slide and I guess that my thinking would be probably correct.
Because the Front-end and the Execution-pipe are decoupled, the number of the Front-end stages of the pipeline are not counted.
That is, 4 stage integer pipeline means the Execution-pipe of the integer (i.e. "Register File or Decode", "Shift", "ALU" and "Writeback").
Regarding the Floating point pipe, "Float Register File" stage is added and the total pipeline stages would become 5.