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How long are the Cortex-M7 pipeline stages?

Hello experts,

recently ARM updated the Cortex-M7 information.

I think the biggest topic would be that the pipeline details were opened.

The new information says that the integer pipeline is 4 stage and the floating point pipeline is 5 stage.

However, the past information said that it was 6 stage.

From where this differences came?

I would like to know the concrete explanation for each stage.

What is the first stage, what is the second stage, what is the third stage, what is the fourth stage, and so on?

CM7_PIPE1.jpgCM7_PIPLE2.jpg

Best regards,

Yasuhiko Koumoto.

Parents
  • Hello all,

    I don't need the details of each pipeline stage. I just want to know the name of each stage.

    In the old slide, I can read as the followings.

    1st = Fetch

    2nd = Decode

    3rd = Issue

    4th = Execute #1

    5th = Execute #2

    6th = Write/Store

    In the new slide, I think it as the followings.

    1st = Instruction Decoders

    2nd = Integer Register File

    3rd = Shift

    4th = ALU

    Is it correct?

    I would like to know that the pipeline figure had been drastically changed.

    Also I would like to know the relationship between the old and the new figures.

    Thank you and best regards,

    Yasuhiko Koumoto.

Reply
  • Hello all,

    I don't need the details of each pipeline stage. I just want to know the name of each stage.

    In the old slide, I can read as the followings.

    1st = Fetch

    2nd = Decode

    3rd = Issue

    4th = Execute #1

    5th = Execute #2

    6th = Write/Store

    In the new slide, I think it as the followings.

    1st = Instruction Decoders

    2nd = Integer Register File

    3rd = Shift

    4th = ALU

    Is it correct?

    I would like to know that the pipeline figure had been drastically changed.

    Also I would like to know the relationship between the old and the new figures.

    Thank you and best regards,

    Yasuhiko Koumoto.

Children