How long are the Cortex-M7 pipeline stages?

Hello experts,

recently ARM updated the Cortex-M7 information.

I think the biggest topic would be that the pipeline details were opened.

The new information says that the integer pipeline is 4 stage and the floating point pipeline is 5 stage.

However, the past information said that it was 6 stage.

From where this differences came?

I would like to know the concrete explanation for each stage.

What is the first stage, what is the second stage, what is the third stage, what is the fourth stage, and so on?


Best regards,

Yasuhiko Koumoto.

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