System Bus in ARM Cortex-M4

In what situations will separate data buses ( D and S) for ARM Cortex-M4 improve performance? Also, are there any benefits of von Neuman support along with the core Harvard Architecture?

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  • Thanks yasuhikokoumoto and jensbauer for ur replies. Both of u very well explained the significance of a data bus along with an instruction bus.

    But i would like to know more about why two data buses instead of one?  Is it entirely for DMA support for cases like the one explained by jensbauer or there are other situations as well.

    Regarding Von Neuman architecture my point is that ARM Cortex M4 has Harvard architecture

    but suppose we access instructions and data from a memory above 2000_0000 , what we get is a von Neuman kind of architecture, in the sense all instructions and data appear on a single bus (SYS bus).

    So my doubt is whether this feature has a special intention in terms of architectural benefit?

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  • Thanks yasuhikokoumoto and jensbauer for ur replies. Both of u very well explained the significance of a data bus along with an instruction bus.

    But i would like to know more about why two data buses instead of one?  Is it entirely for DMA support for cases like the one explained by jensbauer or there are other situations as well.

    Regarding Von Neuman architecture my point is that ARM Cortex M4 has Harvard architecture

    but suppose we access instructions and data from a memory above 2000_0000 , what we get is a von Neuman kind of architecture, in the sense all instructions and data appear on a single bus (SYS bus).

    So my doubt is whether this feature has a special intention in terms of architectural benefit?

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