Let me see if I have this straight...
By "self-hosted debugging", I mean the ability for code running on the CPU itself to set and handle breakpoints, single-stepping, etc. This was common in early CPUs - the 8080 and Z80 could do it, the 68000 series had not problems, etc. (they also didn't have hardware support for breakpoints/etc. Instead, you actually replaced instructions with an instruction that would cause a SW trap, and the trap handler would do appropriate magic to execute the missing instruction...)
Now, it looks like you can do this sort of thing on an ARM v7m chip (CM3, CM4, CM7) via the "debug monitor" state.
But the ARM v6m (CM0, CM0+) doesn't have the "debug monitor" state (even if it does have the the debug extension.) It only has "debug state", and the way I'm reading the docs, debug state means that things are only manipulated via an external DAP. Breakpoint exceptions when the DAP port isn't connected cause a hard fault. Hard faults aren't generally considered "recoverable" because they don't save enough context to analyze. Does that mean that handling a BKPT exception in software is impossible on v6m? (It looks vaguely like the BKPT unit itself saves additional context that might be enough, IF that info can be accessed by SW...)
Does anyone know of any existing self-hosted debuggers (or gdb remote stubs) for Cortex-M chips?
I used watchpoints on Cortex-M3/4/7 for stack protection w/o debugger.
But due to the Cortex-M0 limitation the same code works only with attached debugger and it generates a normal hard-fault instead of a debug exception.
But I never tried breakpoints.
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