IT instruction doing funny things?

Hello all

I have an S32G (bundled with 3 M7F cores) and a GHS compiler to process the following code that erases the BSS region

while (b != a)
        {
            t = OFFSET + (char *)(*b++);
            v = *((ptrdiff_t *) b); b++;
            n = *((size_t    *) b); b++;

            if (t + n != t)
            {
                (*memsetp)(t, v, n);
            }
        }

(The weird comparison t+n!=n is made instead of n!=0 to force the compiler to do the same thing following a different strategy)

The compiler generates this assembly

Where the cmp at 0x34100d76 is performing the comparison between t+n and t, then as you can see in the image the Z bit is set, so itt ne should prevent the two following instructions from being executed (as NE means Z==0). But as you can see the execution flow follows through 0x34100D7A and ..7E

Obviously I am missing something here, but I dont know what it is. I checked that the instructions were properly decoded against ARMv7-M Architecture Reference Manual

BR

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