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Potential limitations for MPU regions attributes?

Hello,

I am working on a SoC with several Cortex M7 cores. It has SRAM mapped to region 0x2000_0000 and DDR mapped to 0x6000_0000 -> 0xDFFF_FFFF.

It seems that configuring the 4 regions of DDR to cached normal memory is triggering an HW bug which freezes the whole chip. Even the debugger get disconnected. Note that I do not need to access the DDR to raise the problem. Just configuring the MPU then running code in SRAM will, after a random delay, trigger the bug.

Is there any limitation to the attributes I set when configuring the MPU?

I would say only the system space in 0xE000_0000 has fixed attributes, but I have a doubt because if I refer to ARMv7-M arch ref manual, I can for instance find this:

"B3.1 The system address map"

"A declared cache type can be demoted but not promoted"

I am not sure here if this is just a limitation during runtime or an absolute limitation that forbids enabling the cache for partitions at 0xA... and 0xC... as they are not enabled in the default address map.

Also, the documentation indicates that the DDR is normal memory, but is there any problem if I keep it configured by default as device memory (without taking into account non reordered accesses inherent to this configuration)?

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