This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

MPU on ITM Address Range

Hello,

I am trying to enable MPU on peripherals to allow them only for only privileged access and trying to access from an unprivileged thread.

All address range works well except ITM(Instrumentation Trace Macrocell) address space. 

I am working on STM32F429-Cortex M4, I am not sure is it about ST's MCU or Arm Cortex M Core

I am setting the MPU for the whole peripheral range at a time.

The ITM address is 0xE0000000

If "address < 0xE0000000" MPU Works
If "0xE0000000 < address < 0xE0010000" Unprivileged Thread Can Read : FAILURE
If "0xE0010000 < address < 0xE0100000" BUS Fault
If "0xE0100000 < address" MPU Works

Is there any limitation on MPU for ITM address space?

Kind Regards,

Murat

  • The MPU cannot modify some attributes of the default memory map

    • The System space (0xE0000000 or higher) is always marked as XN, Execute Never
    • Accesses to the Private Peripheral Bus (PPB) (0xE0000000 to 0xE00FFFFF) always use the default system address map
    • Exception vector reads always use the default system address map

    If the ITM is disabled or not implemented, a write to a stimulus port must not cause a BusFault exception. This ensures the ITM is transparent to application software.

    The Trace Privilege Register defines whether each group of eight Stimulus Port registers (32 implemented in Cortex-M4), and their corresponding Trace Enable Register bits, can be written by an unprivileged access. Unprivileged code can always read the Stimulus Port registers.