Cortex-M4 interrupt occures right after it's disabled

Hi! I use STM32F417 with cortex-M4 core in my project. I found that a timer interrupt occures just after 2 instruction after disabled through peripherial register. How iis it possible? Assembler code (Interrupt disable regiter - is memory mapped peripherial register)

0x080016B4 49C0      LDR           r1,[pc,#768]  ; @0x080019B8
0x080016B6 8008      STRH          r0,[r1,#0x00] ;DISABLE INTERRUPT IN IER REGISTER
   146:     preemtp_disabled++; 
   147:     //TIM4->DIER |= TIM_DIER_UIE; 
0x080016B8 48BF      LDR           r0,[pc,#764]  ; @0x080019BC
0x080016BC 6800      LDR           r0,[r0,#0x00]
0x080016BE 1C40      ADDS          r0,r0,#1 ; <<<THIS IS A RETURT ADDRESS FROM INTERRUPT

May be it's a pipilene prefetching and reordering? Pipeline prefetsches 3 instructions, reorder them and advance pc counter, just in this time an interrupt occures. I was stopped at breakpoint in interrupt handler and interrupts has been disabled yet, and pc in exception frame points to 0x080016BE. I try to insert ISB instruction after clear interrupt disable bit, and after that cant reproduce this behavior any more. May be it works for me, or an error has not reproduced yet.. Thanks.