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I have a doubt about memory addresses ¿Any expert?

Hi,

First of all, I apologize for my English level, I am not a native speaker. I hope you can understand me 

  • EXPLANATION:

1) PHYSICAL WORLD / HARDWARE : In 32 bits microcontrollers, the memory digital circuits have 1 memory address per 4 bytes. In other words, if you would want to store a "char" variable in the byte 0 of the memory, you will use the same "real or physical" memory address than if you would want to store other "char" variable in byte 1 of the memory.  ( 4 bytes shares the same physical memory address )

2) SOFTWARE : When you store two "char" variables in memory and print their memory address using C language, you can see that each byte have different memory addresses. For example:

- char a = 'a'; // use memory address 0x00000000

- char b = 'b'; // use memory address 0x00000001

  •  MY QUESTION:

Suppose I am at a memory address that contains 4 bytes (HARDWARE ADDRESS: 0x00), and I only want to write or read 8-BIT data in the third byte (SOFTWARE ADDRESS: 0x03):

- I would like to know how the hardware or the digital electronic circuit design of the memory deals with this (in ARM Cortex-M architecture). ¿Are there any additional signals besides the 32 bit memory address to handle this?

Thank you!

Parents
  • Your first statement "32bit processors have 1 memory address per 4 bytes" isn't true.

    In every modern 32bit architecture I can think of, there is one memory address per 4 bytes,  The memory itself may be 4 bytes wide per "physical address" (or even wider, given cache and multiple-channel memory), in which case the low bits of the CPU address are used to select which byte with the memory word is actually used, but this is typically handled internally by the bus logic.

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  • Your first statement "32bit processors have 1 memory address per 4 bytes" isn't true.

    In every modern 32bit architecture I can think of, there is one memory address per 4 bytes,  The memory itself may be 4 bytes wide per "physical address" (or even wider, given cache and multiple-channel memory), in which case the low bits of the CPU address are used to select which byte with the memory word is actually used, but this is typically handled internally by the bus logic.

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