I was looking into the debug and trace features in the Arm Musca Board A1, which implements the Corelink SSE 200 IP (dual core Cortex M33, each with a three-stage pipeline), I came across the data watchpoint and trace and his ability to estimate how many instructions have been executed.
My doubt is:
Correct me if my line of thought is wrong cause I am not 100% sure if this is correct.
Note sure if it helps, but the "formula" for calculating instructions is:
Measuring data taken with the DTW cycle counters.Instructions:isns = cyccnt - cpicnt - exccnt -lsucnt - sleepcnt + foldcnt;
Be aware, all counters besides cyccnt are only 8 bit!
Thank you! I am already using them. I was wondering if it is possible to relate executed instructions with memory accesses. For example: If the core executed +- 1000 instructions in one second and it fetches 32 bits each time, and in Thumb code instructions can be 16 or 32 bits.So let's say that each fetch is 1.5 instructions, so 1000 * 32 bits / 1.5 ~= 21332 Bits = 2666 bytes read in one second ?!?! I know this is probably really dumb but I was just wondering x) (Pls note that there are a lot of assumptions here)
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