Instruction Count and Memory Access


I was looking into the debug and trace features in the Arm Musca Board A1, which implements the Corelink SSE 200 IP (dual core Cortex M33, each with a three-stage pipeline), I came across the data watchpoint and trace and his ability to estimate how many instructions have been executed.

My doubt is:

  • Can I relate the number of instructions executed with memory access. From what I read, but I am not sure, the core fetches 32 bit of data and most instructions are 16 bits. My line of thought was: use one of the DWT counters (DWT_CPICNT) that tells me, +-, how many stalls have been, plus the number of instructions that have been executed. If I know how many instructions are fetched per memory access I get in some "weird" way the number of memory accesses ?!?!

Correct me if my line of thought is wrong cause I am not 100% sure if this is correct.


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