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What happens to the Instructions already in pipeline when interrupt occurs ?

Vijay Kumar Prathipati

Hello Community,

Recently I was going through some code and has this doubt.

My Pseudocode

============

CPSID I - Disable interrupts

Do critical work

CPSIE I - Enable interrupts

Do non critical work.

After I enabled interrupts and if there is pending interrupt , Does the exception handler will execute right after CPSIE I instruction ? What happens to the instructions that are already there in pipeline ?  I am looking for CM0/CM0+ behavior.

Regards.

Vijay.

Parents
  • 0 in reply to a.surati
    a.surati said:
    Perhaps RTOS? Or drivers of some sensitive devices? Or tightly-packed, highly-efficient code sequences with CPSIE/D that overlap with interrupt processing, and such an overlap must be avoided?

    A design which relies heavily on such low-level behavior is prone to fail sooner or later.

    For test reason this information is ok, but I would not trust any product being designed like this.

    The demo scene does such (tag: Atari ST, border opening), but no RTOS.

    The only real use case I see is the "enable; isb; disable" snippet, to allow interrupts at well defined points.

Reply
  • 0 in reply to a.surati
    a.surati said:
    Perhaps RTOS? Or drivers of some sensitive devices? Or tightly-packed, highly-efficient code sequences with CPSIE/D that overlap with interrupt processing, and such an overlap must be avoided?

    A design which relies heavily on such low-level behavior is prone to fail sooner or later.

    For test reason this information is ok, but I would not trust any product being designed like this.

    The demo scene does such (tag: Atari ST, border opening), but no RTOS.

    The only real use case I see is the "enable; isb; disable" snippet, to allow interrupts at well defined points.

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