Cortex M0+, AHB state during Exception

I have a STM32L031 (Cortex M0+).

I need to ensure that the SRAM is not modified externally by the DMA during a (very short) cyclic SRAM test.

My first thought was to force an Exception, block the AHB, do the test and return. A short delay will not cause any problems with the DMA transfer, the buffering can handle that.

But, I can't find any information AHB and bus master / blocking during exceptions.

Does anyone know if this is feasible?

Can any one point me to the correct place where I can find the information?

Does anyone have another idea on how I can block the DMA access to the SRAM for a few CPU cycles?

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