I'm trying to configure Cypress TII MCU, powered by CM4 core, to forward the core halt state to be routed to WDG module.
This is solution advised by the MCU support, but this actually fail to work (fail only when the debugger is disconnected), and the failure may be related to the CM4 core, or actual SoC integration.
So generally aim of the config is to force watchdog IP to pause when the specific core is halted during debugging (debug state of core).
In my entry point code of CM4 core I try to do the follwing:
#define CM4_CTICONTROL (*((volatile uint32_t*)(0xE0042000)))
#define CM4_CTIINTACK (*((volatile uint32_t*)(0xE0042010)))
#define CM4_CTIINEN(n) (*((volatile uint32_t*)(0xE0042020 + 4 * n)))
#define CM4_CTIOUTEN(n) (*((volatile uint32_t*)(0xE00420A0 + 4 * n)))
CM4_CTICONTROL = 0x1;
CM4_CTIINEN(1) = 0x1;
CM4_CTIOUTEN(1) = 0x1;
TRC_CTICONTROL = 0x1;
TRC_CTIINEN(4) = 0x1;
TRC_CTIOUTEN(6) = 0x1;
And the point is, that accessing the CTICONTROL register finish with Bus fault exception (PRECISERR and BFARVALID set in CFSR).
The BFAR contains value of 0xE0042000 (CTICONTROL register). And the stacked PC value is definitely pointing to the store instruction, related to writing at address 0xE0042000.
What is very interesting the CTICONTROL succeeds when running the code under debugger session (in my case JLink connected with Ozone debugger).Generally the code executes in privileged thread mode, I also tried configuring the register from handler mode, no effect (bus fault as well).
In coresight reference manual I can see that "There are no usage constraints" for CTICONTROL register.
Could anyone advise, what may be the reason (except erroneous SoC integration, and accessing in unprivileged mode) for writing External PPB address range failing with bus error?
What is also interesting, that in case of the STM32F4x MCU I've tested the problematic bus fault hasn't occured in described scenario.
No progress in the topic, so maybe the post should be moved to some other forum (SoC Design)?
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