Hey,
As I am exploring the tracing capabilities present in the Cortex M33, there are some things that I am not able to understand fully, such as the connection between ETM and the tracing sinks. As I read, more doubts emerged, and the more confused I got. So what I wanted to know is:
Cheers
ETB - Buffer in the Trace CellMTB - Interface to the SoC SRAM (depends on the SoC where it goes).
Hey again,
Thanks for your reply! So one question remains. Can the host/running Core access the Embedded Trace Buffer? As much as I searched, I can`t find any memory mapping for the ETB. Thus that means that it is only accessible by a debug probe to download the trace data?
Note: I am using a board that implements the Arm CoreLink SSE-200 subsystem.
I don't thing it can access. Bcoz it can damage the entire system then UPSers
Why should it damage anything?
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