I am trying to find the location of the register where the timestamp generator can be enabled on a Cortex-M4 processor.
In the CoreSight SoC Technical Reference Manual on page 3-210 it is mentioned that the register (CNTCR) is in the PSELCTRL region (see image). However, I am not able to find the base memory address of this PSELCTRL region.
Can I find this address somewhere the ROM table that indicates the implemented debug components? But then how do I know which ID it is?
Or is it defined in some datasheet?
Thank you for any help.
The IDs dare also described in the manual. E.g. 3.19.4 ID4 = 0x4.AFAIK, you need to scan the ROM table. There is no specific order.
Thank you for your reply.
I tried to read the ROM table at 0xe00ff000 as specified in the ARMv7_M Architecture Reference Manual (see image)
The result is the following:
But how can I now, based on this, find out if the TSGEN (timestamp generator) is present on the STM32L433CC chip? And if it is what is its address?
I guess the PIDs I read out are just the PIDs of the debug component itself but not of TSGEN.
I don't understand the concept of PIDs and CID and can't find a tutorial for their use.
STM32L433CC does not have the TSGEN, at least it is not listed in the manual.
AFAIK, the ROM table at 0xe00fF000, for each entry you have to look up the PIDs and compare them against the ones from the CoreSight manual in order to know what it is.
For example Jlink outputs this on a stm32l552:
ROMTbl @ E00FE000
ROMTbl: E00FF000, CID: B105100D, PID: 000BB4C9 ROM Table
ROMTbl @ E00FF000
ROMTbl: E000E000, CID: B105900D, PID: 000BBD21 Cortex-M33
ROMTbl: E0001000, CID: B105900D, PID: 000BBD21 DWT
ROMTbl: E0002000, CID: B105900D, PID: 000BBD21 FPB
ROMTbl: E0000000, CID: B105900D, PID: 000BBD21 ITM
ROMTbl: E0041000, CID: B105900D, PID: 002BBD21 ETM
ROMTbl: E0042000, CID: B105900D, PID: 000BBD21 CTI
ROMTbl: E0040000, CID: B105900D, PID: 000BBD21 Cortex-M33
Dumping memory at 0xe00fe00:
E00FE000 = 00001003 FFF42003 1FF02002 1FF02002
E00FE010 = 00000000 00000000 00000000 00000000
=> one entry at 0xe00fe000+0x1000 and one at 0xe00fe000+0xfff42000
Entries 2 and 3 are not present (LSB == 0)
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