Interrupt vector calculation with VTOR.

Hi Cortex-M architects or experts,

I have a question. Is the interrupt vector calculated by not ADDed with VTOR but ORed with VTOR? There is a post in the Freescale Kinetis Community as "Vector Table Offset - is this expected behaviour??" (https://community.freescale.com/thread/337498). His post shows it is ORed. This would be uncertain even if I read ARMv7M Reference Manual. I would like to clarify the fact.

Best regards,
Yasuhiko Koumoto.

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  • I would add additional information. Those description might indicate that an interrupt vector address would be calculated by or-ing with VTOR. I investigated ColdFire, SuperH2 and V850E2. Their interrupt vector is calculated by adding to the vector base register. Is ARM only strange?


    "ARMv7-M Architecture Reference Manual" B1.5.3 The vector table

    The Vector table must be naturally aligned to a power of two whose alignment value is greater than or equal to (Number of Exceptions supported x 4), with a minimum alignment of 128 bytes.

    "Cortex-M4 Devices Generic User Guide" 4.3.4. Vector Table Offset Register


    The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64.

  • Hi yasuhikokoumoto san,

    Disclaimer first: I am not Cortex-M architect, neither an expert though though your question is addressed to one.

    I don't think there is ORing here. Basically the VTOR contains offset to the start of the vector table. By default the VTOR is 0 and therefore the vector table is located at 0x0000 0000. Starting address being the initial stack pointer value.

    Any interrupt/exception vector would be calculated by adding the exception number to the offset and reading the contents of this memory location.

    The alignment restriction makes the VTOR being written a value of next highest power of 2 from the max number of entries in the table.

    Not sure if this helps you.

    Thanks,

    Gopal

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  • Hi yasuhikokoumoto san,

    Disclaimer first: I am not Cortex-M architect, neither an expert though though your question is addressed to one.

    I don't think there is ORing here. Basically the VTOR contains offset to the start of the vector table. By default the VTOR is 0 and therefore the vector table is located at 0x0000 0000. Starting address being the initial stack pointer value.

    Any interrupt/exception vector would be calculated by adding the exception number to the offset and reading the contents of this memory location.

    The alignment restriction makes the VTOR being written a value of next highest power of 2 from the max number of entries in the table.

    Not sure if this helps you.

    Thanks,

    Gopal

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