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Tollchain for Cortex_M3

Hi.

i am a little bit confused!

what are the known types of tollchans for Cortex M for example Stm32?

is the gnu-arm-gcc the same as arm-none-eabi-gcc?

Wtah about WinARM?

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  • The naming  for GCC based toolchain is  :

    ".. loosely named using a convention of the form arch[-vendor][-os]-abi. "

    gnu-arm-gcc is thus probably ARM GCC spin-off,  no OS (baremetal).  I'm not sure but this is probably their old naming, not how Linaro names it.

    arm-none-eabi-gcc is thus target ARM no vendor specific EABI bare-metal GCC.

    On ABI / EABI , see here: 

    https://en.wikipedia.org/wiki/Application_binary_interface

    On GCC toolchain naming see some notes here :

    https://web.eecs.umich.edu/~prabal/teaching/resources/eecs373/toolchain-notes.pdf

    An "arm-none-eabi-gcc" should compile for any ARM/ Cortex target it supports, independent of vendor specific target - like Stm32.  However, as you understand, there will be your SoC or board specific initialization which depends on your chip , such as memory layout. So for one, a vendor may provide target chip C runtime init code, and other board specific initialization. To make user's life easier.  Or, you write one yourself.

    Hope that makes it a little bit clearer for you.

Reply
  • The naming  for GCC based toolchain is  :

    ".. loosely named using a convention of the form arch[-vendor][-os]-abi. "

    gnu-arm-gcc is thus probably ARM GCC spin-off,  no OS (baremetal).  I'm not sure but this is probably their old naming, not how Linaro names it.

    arm-none-eabi-gcc is thus target ARM no vendor specific EABI bare-metal GCC.

    On ABI / EABI , see here: 

    https://en.wikipedia.org/wiki/Application_binary_interface

    On GCC toolchain naming see some notes here :

    https://web.eecs.umich.edu/~prabal/teaching/resources/eecs373/toolchain-notes.pdf

    An "arm-none-eabi-gcc" should compile for any ARM/ Cortex target it supports, independent of vendor specific target - like Stm32.  However, as you understand, there will be your SoC or board specific initialization which depends on your chip , such as memory layout. So for one, a vendor may provide target chip C runtime init code, and other board specific initialization. To make user's life easier.  Or, you write one yourself.

    Hope that makes it a little bit clearer for you.

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