Cortex M4 exception return sequence

Hi,

I think I am just getting confused with this even if (or because of) I read the book and manuals again and again.

At exception entry, the processor saves R0-R3, R12, LR, PC and PSR on the stack. Saving PC means that the address of the instruction to be executed next after return from the exception handler is saved on the stack. However, the documentation also says that LR is updated with EXC_RETURN and that when the EXC_RETURN value is loaded to the PC, the exception return sequence begins.

So, the confusion is - it is the stacked PC value which should be loaded to the PC to return to the place where it left to attend the exception handler. If the PC is loaded with EXC_RETURN value, it is not a valid address but that only the lower 5 bits indicate which stack was used and the return mode (thread/handler) etc.

Or is it that the loading of PC with EXC_RETURN is then followed up by loading of the PC with the stacked PC value?

Can someone please help clearing this confusion?

Thanks,

Gopal

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  • As you say the EXC_RETURN values are special values that are recognized by the hardware rather than proper pc values. Loading an EXC_RETURN value into the program counter initiates the hardware sequence that does the reverse of the sequence which happened when the interrupt came in. That reverse sequence will then load the actual pc to resume at. You don't explicitly load the various registers, that is all done automatically by the return sequence.

    Doing the entry and return in hardware allows the processor to not actually do the return sequence if there is a pending interrupt but immediately start handing the new interrupt instead without having to load  the registers on return and then store them again before entering the new interrupt handler..

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  • As you say the EXC_RETURN values are special values that are recognized by the hardware rather than proper pc values. Loading an EXC_RETURN value into the program counter initiates the hardware sequence that does the reverse of the sequence which happened when the interrupt came in. That reverse sequence will then load the actual pc to resume at. You don't explicitly load the various registers, that is all done automatically by the return sequence.

    Doing the entry and return in hardware allows the processor to not actually do the return sequence if there is a pending interrupt but immediately start handing the new interrupt instead without having to load  the registers on return and then store them again before entering the new interrupt handler..

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