Hi dear friends,
I want to investigate whether it is better to activate caches in stm32F7 or not.
For this purpose, I have studied stm32f7 reference manual and I have some questions about what I have read:
1. According to the reference manual, data coherency between caches and Flash memory is the responsibility of the user code. However, I do not know how the user code can guarantee this coherency.
2. Again according to the reference manual: "To release the processor full performance, the accelerator implements a unified cache of an instruction and branch cache which increases program execution speed from the Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ARTaccelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 216 MHz. The ART accelerator is available only for flash access on ITCM interface. " Again I do not understand its meaning.
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