Problems with interrupting LDM/STM Cortex M4?

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.

The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}

The ICI bits at the time of the interrupt equal 7. This means that the STM was partially completed, and should be resumed starting at r7.

However, if I look at the stack at the time of the interrupt, I see 4 words were written by the interrupted STM, namely r4, r5, r6, and r7. This means that

r7 will be written again when the processor resumes the STMDB instruction.

This does not happen all the time. But it forces me to disable interruption of multicycle instructions.

Parents
  • Hi, is it a problem for you? However, "ARMRv7-M Architecture Reference Manual" says "The continuation state of the LDM or STM is held in the ICI bits in the EPSR . It is IMPLEMENTATION DEFINED when interrupts are recognized, so the use of the ICI bits is IMPLEMENTATION DEFINED." in the chapter B1.5.10. The phenomenon would not be surprised. That is, it is not guaranteed of each register to be accessed only once.

    Best regards,
    Yasuhiko Koumoto.

Reply
  • Hi, is it a problem for you? However, "ARMRv7-M Architecture Reference Manual" says "The continuation state of the LDM or STM is held in the ICI bits in the EPSR . It is IMPLEMENTATION DEFINED when interrupts are recognized, so the use of the ICI bits is IMPLEMENTATION DEFINED." in the chapter B1.5.10. The phenomenon would not be surprised. That is, it is not guaranteed of each register to be accessed only once.

    Best regards,
    Yasuhiko Koumoto.

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