vldr d16, [r7, #200] ; 0xc8 causes Hard fault (Forced)

Process: Cortex M33 [Lpc55s69 (cm33_core0) with DSP extension]
Build tool: GNU Tools ARM Embedded/8 2019-q3-update
Debug Environment: MCUXpresso IDE v11.0.1 [Build 2563] [2019-09-01]

From main() the following assembly line is executed:

vldr d16, [r7, #200] ; 0xc8
r7 = 0x2003fea0 prior to execution ends up in HardFault_Handler() at startup_lpc55s69_cm33_core0.c:451 0x1ea

Prior to main() getting called, From the Reset handler SystemInit() is called, code shown below (code from system_LPC55S69_cm33_core0.c):

void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */

SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */

SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */

#if defined(__MCUXPRESSO)
extern void(*const g_pfnVectors[]) (void);
SCB->VTOR = (uint32_t) &g_pfnVectors;
extern void *__Vectors;
SCB->VTOR = (uint32_t) &__Vectors;
/* Optionally enable RAM banks that may be off by default at reset */

debugging disassembly of SystemInit() shows all the lines are exposed & executed all of it, since the flags have all been defined.

I assume SystemInit() should Enable the FPU.

1. How to know if the M33 processor current running context is
a. Secure or none-secure.
b. privileged or not privileged
c. Thread or handler
Is there a CPSR type register on the M33 core (Please bear with me, I am a older timer way back from ARM7TDMI core and I am not familiar for the cortex cores) to show the current Program status, so we can understand what privileged, security the current context is on when debugging?

2. How to know the M33 core FPU status, if it is enabled or disabled. Is there a register to get its current Enable status?

3. I assume the SystemInit() should be called from secure & privileged, so it can access these registers to enable the FPU, I assume this is the case, answer to #1 question will positively confirm it. I assume if there was a problem, the processor should have caused a security exception, is that correct?

4. If FPU was enabled, then anything else is needed before using the FPU instructions in the code?

some note includes the following instruction:
ISB ; Reset pipeline now the FPU is enabled.

I find them missing in the SystemInit(). Are these needed? I did try including them prior to executing the VLDR instruction:

CPACR |= (0xf << 20); // enable access to FPU
Val = (int16x4_t)vld1_lane_s32(((const int32_t *)(&gMyInout[k])), (int32x2_t)Val, 0);

Adding the above lines did not help either, still ends up in the Exception handler.

Please point me to what went wrong.


  • The CFSR will give you more clues about what type of fault is taking place. At a glance, the FPU config looks correct to me. One other thing you might want to check is the value of $r7 ... I'm not sure what type gMyInout but if the vldr data access is not word aligned, it would also generate a fault.

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