I stumbled upon this page which brought up some questions:
The obsfucated RTL is synthesizable and should be cycle accurate. I don't see any technical reasons why the RTL could not be verilated and run as a simulator. I understand that you would need to add peripherals to the buses to make it useful along with some glue to handle JTAG. Am I missing something or has no one gone down that path?
On the licensing front I know I agreed to a click-thru license to download the designstart package but I can't seem to locate it. Does anyone have a link or know what the distribution restrictions of a verilated binary produced from the obsfucated RTL are?
Bonus question: Does anyone have a rough estimate of the frequency that the ARM cycle model can run at on a modern PC? 10kHz? 100kHz? 1MHz?
Just to clarify my intentions I plan on using this in-house as a flexible virtual system platform. For JTAG it should be pretty easy to write a "bitbang server" and then use openocd as the GDB server. There will be two layers of peripherals, both loadable as runtime plugins. The AXI bus peripherals will have a memory interface, they can optionally export "ports" which will connect to secondary peripherals. These ports would correspond to fixed interface types (UART, SPI, I2C, etc). The secondary peripherals would then be LCD controllers, sensors, SD card, etc.
Of course this would be more useful if it could be used (and improved upon) by other developers. I suppose worst case I can release everything else and have them drop in cortexm3ds_logic.v before compiling. I'd be curious to hear if anyone else is interested in this? It likely would be much slower than the ARM fast model (which I tested and appears to run around 4 million instructions per second.
For those interested: github.com/.../cm3-oracle
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