Fail to connect with CM0DSEvel

I have tryed to make SWD connect to Cortex-M0 DesignStart Eval by STLink2, but it was unsuccessful.

The SW Device showed information as this picture.

I chose  AHB_ROM_FPGA_SRAM_MODEL and AHB_RAM_FPGA_SRAM_MODEL be the MYM_TYPE

  • Assume you are using an FPGA to prototype it:

    - make sure you have added suitable tristatre buffer at top level and the polarity of the tristate buffer enable is correct.

    - make sure you have setup clock constraint to SWDCLK, and make sure from your synthesis log that the contraints are applied sucessfully.

    - check the voltage level requirement of the STLink2 - Some FPGA I/O level might be a bit too low.

    Hope this helps.

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