Could you help me to solve the problem.Do you have the code to verify the thumb instruction ? If have,the code can check any corner the functions of thumb instructions
Thank you very much!
It is similar to normal DFT scan test, but the capture cycle (gap between last shift to capture clock edge) is using normal clock speed.
https://www.eetimes.com/document.asp?doc_id=1217753
Never do this before,How to do at-speed test with scan chins?
Can you do at-speed test with scan chains?
This is a timing issue, when it runs at lower frequency,the result of SUBS R2,R2,R4 is correct.So we want to pick up those bad chips by running code. But how to pick up?
the chip is truely bad,only SUBS is wrong,others functions are very good, and he clocks of chip is good. we can make sure that the chip is a timing issue
I ran into this on a chip. I had accidentally hooked up a GPIO to 5V, after doing this I would get random hard faults. It was also having trouble setting the CPU clocks. At the end of the day I swapped processors and the problem went away.
Don't under estimate that the chip may be bad or the clocks got noise.
Is this a timing path issue? Does it fail when running at lower frequency?
In general we expected DFT to pick up this kind of issues. There are some limitations with DFT, for example, timing violations might not be picked up by DFT because scan clock usually run slower, and defects could be hidden as clock signal's characteristic could be very different in scan mode. But test coverage of software tests are usually much lower than DFT. In general, DFT is the recommended test method.
regards,
Joseph
the memory and flash of bad chip is good , We have tested them. We have tested CM0 logic by DFT, but is ok. Only the instructions (SUBS R2,R2,R4 ) is wrong, no matter the SUBS in SRAM or FLash
For chip production tests, usually for logic (i.e. the processor and the processor system logic excluding RAM) should be tested using scan tests. Before tape out, you should also run LEC (Logic Equivalent Checking) to ensure that that netlist matching the RTL.
For memory macros, you can add memory BIST (this is done outside of processors). You need to check the EDA tool manuals on how to do that. You could run software based memory tests, but there is an issue - if the chip is bad, how can you be sure the software to test memory is running correctly?
If you google for "memory testing algorithms" you should find plenty of resources.
We have run the code on an FPGA,the result of R2 is 0x08. But only the one chip is bad, others run the same code is OK。We try to pick pu bad chips which have the same problems, when test chip in FT. But we don't know how to check the functions of CM0,Can you give me some methods?
What is the initial state for R2 when you run the test? ( D2 ? ;-) )
Is it an FPGA prototype?
Hi Andy,
That's true. But as the question is about memory testing, I would expect the program would have enabled the memories before starting the test ;-)
(Note: for memories it is less common for it to be disabled at start. e.g. imagine you want to place the stack at the top of the RAM and by default that memory range is disabled, your SystemInit and C startup code won't be able to run).
Joseph Yiu said:understand the memory map of the device to see if the error is caused by an access to illegal address
hyue: in addition, note that (some?) chips will give a hardfault if you try to access a peripheral which has not been enabled.
So, as well as ensuring that an address is legal, you also have to ensure that it is in a valid state.
Some chips allow you to turn off parts of the memory to save power - I guess that could also be a source of a hardfault if you try to access disabled memory ... ?
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