Could you help me to solve the problem.Do you have the code to verify the thumb instruction ? If have,the code can check any corner the functions of thumb instructions
The Hardfault may be possibly caused by:
1. The access address is not aligned to its access size.
2. The external bus-matrix-slave responses with error response.
I think the corner case will be different from different usage, while arm has verified the functions of CM0
Can you give the vrefiy code ? or the way to verifiy the functions of CM0
Hi there,
Haiyan already gave you good information about possible cause for the HardFault.
To debug the issue, you should:
- generate disassembly code of the program image to see what instruction is being execute at the point of failure
- see the state of registers to see exactly which address you are accessing, and if there is any address alignment issue
- understand the memory map of the device to see if the error is caused by an access to illegal address.
From there you should be able to pin point the cause of the HardFault - typically software bugs like attend to generate unaligned access or invalid pointer location (end up with bus error).
We use many verification methodologies for processor verification. Unfortunately many of our verification technologies requires specialize verification environments (e.g. simulations, formal verification) and these cannot be use in physical chip devices (especially the memory size and system characteristics is limited in these devices). If you want to learn more about CPU verification, you are welcome to join Arm
https://www.arm.com/company/careers
regards,
Joseph
#pragma location = 0x0001bf0
__root const int16_t TAB_SoftVer[21] ={0,-1,-2,3,4,5,6,7,8,9,10,1,2,3,4,5,6};
//const INT16U TAB_SoftVer[14] @"romdata" ={0x0000,0x1111,0x22222,0x3333,0x4444,0x5555,0x6666,0x77777,0x8888,0x9999,0xaaaa,0xbbbb,0xcccc}; //软件版本(内部用)
__no_init INT8S Ram_Dat[5]@ 0x20000100;
Ram_Dat[0]=-2;
Ram_Dat[1]=-1;
Ram_Dat[2]=0X69;
Ram_Dat[3]=-5;
Ram_Dat[4]=0X66;
__asm(
"NOP\n"
// "NOP\n"
"LDR R4,RAMDAT_ADDR\n"
"LDR R0,ROMDAT_ADDR\n"
"LDRSB R2 ,[R4,R2]\n"
"MOVS R3 ,#3\n"
"LDRSB R4 ,[R4,R3]\n"
"SUBS R2,R2,R4\n"
"LSLS R2,#24\n"
"ASRS R2,#23\n"
"LDRH R2,[R0,R2]\n"
"RAMDAT_ADDR: DC32 0x20000100\n"
"ROMDAT_ADDR: DC32 0x0001bf0\n"
);
the RAMDAT_ADDR is the address of Ram_Dat[5],the ROMDAT_ADDR is the address of TAB_SoftVer.
when it run at "SUBS R2,R2,R4\n" , R2 is wrong , when R2 is 0xFFFFFFF8,R4 is 0xFFFFFFF0, the result of R2 is 0x40800008.
The frequency of core is 11Mhz.
.
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