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How to verify the Cortex-M0 thumb instructions ? I found one chip( RAM &FLASH is OK) when it run LDR relative instructions,the program is in Hardfault。But others run the same code is OK

Could you help me to solve the problem.Do  you have the code  to verify the thumb instruction ? If have,the code can check any  corner the functions of thumb instructions

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  • The Hardfault may be possibly caused by:

    1. The access address is not aligned to its access size.

    2. The external bus-matrix-slave responses with error response.

    I think the corner case will be different from different usage, while arm has verified the functions of CM0

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  • The Hardfault may be possibly caused by:

    1. The access address is not aligned to its access size.

    2. The external bus-matrix-slave responses with error response.

    I think the corner case will be different from different usage, while arm has verified the functions of CM0

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